RIOC 4065 - PowerPC 750 / 74x0-Based CompactPCI Twin Bus Real-Time Processor Board...
- Part Number:
- RIOC 4065
- Model Number:
- RIOC 4065
- Make:
- CREATIVE ELECTRONIC SYSTEMS
- Lead Time:
- Available
- Qty In Stock:
- Available
PowerPC 750 / 74x0-Based CompactPCI Twin Bus Real-Time Processor Board Simple Type: CPU Board
The RIOC 4065 belongs to a new generation of processor boards in terms of architecture and performance, and confirms CES' choice of the winning combination for real-time applications: the PowerPC CPU and the PCI backbone bus. The RIOC 4065 has been designed to provide a function-level compatibility with the RIOC 4064. It is the only PowerPC board offering two onboard PMC slots as well as a PMC extension system. Compared to the RIOC 4064, it provides a massive speed improvement (by a factor of four), due to an extremely fast global memory and a bandwidth control logic, which allocates the throughput between the CPU, CompactPCI and the two 64-bit PCI buses. This latest generation of CES PowerPC boards also features FPGA-based CES-designed PowerPC-to-PCI and PowerPC-to-CompactPCI interfaces to reduce the risk of long-term maintenance.
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Features
- 16 MBytes of Flash EPROM
- Automatic selection of CompactPCI system or peripheral slot
- Brute force power: PowerPC 750 with 1 MByte L2 backside cache or PowerPC 74x0 with 2 MBytes L2 backside cache, at maximum available speed
- BSP for VxWorks® and Linux® with enhanced specifications
- CES-designed direct PowerPC-to-PCI bridges
- CES-designed PowerPC-to-CompactPCI bridge with 16 independent DMA channels on CompactPCI at full CompactPCI speed
- Complete LynxOS® self-hosted development and target packages with CES-enhanced specifications.
- Ethernet full duplex 10 / 100 Base-Tx
- Global memory at cache speed (up to 1 GByte SDRAM at 800 MBytes/s peak)
- Hot-Swap compliant
- JTAG 1149-1 support
- Multiple arbiters for memory bandwidth allocation
- Natively multiprocessor oriented: high-speed synchronization, high-speed message passing, global shared memory, transparent multiprocessing
- Network protocols on PCIs and CompactPCI (TCP/IP)
- New CES-designed programmable Source Interrupt Controller (SIC)
- Optimized bus architecture for maximum bus bandwidth
- PCI 64-bit based on CompactPCI backplane J3 connector. Up to six PMCs controlled by the same RIOC.
- Three concurrent buses at full speed (2 x 64-bit PCI and 1 x 64-bit CompactPCI)
- Twin 64-bit PCI bus architecture
- Two onboard dual PMC slots
- Two serial interface ports
- User-controlled interrupt strategies
Specifications
- Board Type: CompactPCI
Applications
- None Available
Aliases
- None Available
