RIO3 8064 - PowerPC 750 / 74x0-Based VME Twin Bus Real-Time Processor Board...
- Part Number:
- RIO3 8064
- Model Number:
- RIO3 8064
- Make:
- CREATIVE ELECTRONIC SYSTEMS
- Lead Time:
- Available
- Qty In Stock:
- Available
PowerPC 750 / 74x0-Based VME Twin Bus Real-Time Processor Board Simple Type: CPU Board
The RIO3 8064 belongs to a new generation of processor boards in terms of architecture and performance, and confirms CES' choice of the winning combination for real-time applications: the PowerPC CPU and the PCI backbone bus. The RIO3 8064 has been designed to provide a function-level compatibility with the RIO2 8062. It is the only PowerPC board offering two onboard PMC slots as well as a PMC extension system. Compared to the RIO2 8062, it provides a massive speed improvement (by a factor of four), due to an extremely fast global memory and a bandwidth control logic, which allocates the throughput between the CPU, the VME and the two 64-bit PCI buses. This latest generation of CES PowerPC board also features FPGA-based CES-designed PowerPC-to-PCI and PowerPC-to-VME interfaces to reduce the risk of long-term maintenance.
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Features
- 16 MBytes of Flash EPROM
- Brute force power: PowerPC 750 with 1 MByte L2 backside cache or PowerPC 74x0 with 2 MBytes L2 backside cache, at maximum available speed
- BSP for VxWorks® and Linux® with enhanced specifications
- CES-designed direct PowerPC-to-PCI bridges
- CES-designed PowerPC-to-VME64x bridge with independent VME linked list Block Mover Accelerator
- Complete LynxOS® self-hosted development and target packages with CES-enhanced specifications
- Ethernet full duplex 10 / 100 Base-Tx
- Global memory at cache speed (up to 1 GByte SDRAM at 800 MBytes/s peak)
- JTAG 1149-1 support
- Multiple arbiters for memory bandwidth allocation
- Natively multiprocessor oriented: high-speed synchronization, high-speed message passing, global shared memory, transparent multiprocessing
- Network protocols on PCIs and VME (TCP/IP)
- New CES-designed programmable Source Interrupt Controller (SIC)
- Optimized bus architecture for maximum bus bandwidth
- PCI 64-bit based on VME backplane PO connector. Up to six PMCs controlled by the same RIO3.
- Three concurrent buses at full speed (2 x 64-bit PCI and 1 x 64-bit VME64x-LI)
- Twin 64-bit PCI bus architecture
- Two onboard dual PMC slots
- Two serial interface ports
- User-controlled interrupt strategies
- VME64x-LI at over 200 MBytes/s
Specifications
Applications
- None Available
Aliases
- None Available
